1. Field of the Invention
The present invention relates generally to a method for forming a self-aligned contact hole of a semiconductor device and a method for manufacturing a semiconductor device, and more particularly, to a method for forming a self-aligned contact in a semiconductor device which can reduce process failures caused in accordance with the reduction of the design rule and a method for manufacturing a semiconductor device that includes a self-aligned contact.
2. Description of the Related Art
Semiconductor devices have been rapidly developed due to the wide use of information processing devices such as computers, and are typically required to have a large storage capacity and a high operation speed. To meet these requirements, semiconductor technology has been developed so that semiconductor devices have a high integration density, good reliability, and a high response speed.
Because semiconductor devices are highly integrated, patterns formed on a substrate are very small. As a result, the width of the patterns and the space between the patterns must be greatly reduced. As the size of a contact for connecting wirings is reduced, the aspect ratio of the contact increases. Thus, various failures, such as a contact non-open failure, a contact resistance failure, a bridge failure generated between adjacent conductive patterns, and a failure caused by a short channel effect of a transistor, occur in accordance with the reduction of the design rule for manufacturing semiconductor devices. Such failures are difficult to overcome because reducing the possibility of one failure frequently causes another unexpected failure.
FIG. 1A is a cross-sectional view of a prior art device illustrating a self-aligned contact making electrical contact with a source or a drain region of a transistor formed on a semiconductor substrate taken along a direction perpendicular to a gate line (hereinafter, referred to as an X-direction). FIG. 1B is a cross-sectional view of a prior art device illustrating the self-aligned contact making electrical contact with the source or the drain region of the transistor disposed on the semiconductor substrate taken along a direction parallel to the gate line (hereinafter, referred to as a Y-direction).
Referring to FIGS. 1A and 1B, a contact 16 is formed by depositing a conductive material in a contact hole 14 after the contact hole 14 has been formed to expose a portion of the semiconductor substrate 10 between gate structures 12 through a self-aligning process. However, because the interval between the gate structures 12 is narrow, the area of the exposed portion of the semiconductor substrate 10 is very small. The reduction of the area where the contact 16 makes contact with the source or the drain region 11 of the semiconductor substrate 10 increases the contact resistance. As a result of the difficulties in controlling etching processes, the high aspect ratio of the contact hole 14, and the small size of the contact hole 14, insulation material or polymers may frequently remain in the contact hole 14. The insulation material or the polymers remaining in the contact hole 14 may cause failures such as an increase in the contact resistance or a contact non-open failure. To reduce such failures, any material remaining in the contact hole 14 is removed through a reinforced rinsing process after the formation of the contact hole 14.
When a reinforced rinsing process is conducted, occurrence of failures (e.g., a contact non-open failure and an increase in the contact resistance) may be greatly reduced. However, the insulation film 13 between the contact holes 14 may be etched during the rinsing process.
As shown in FIG. 1B, the interval (W) between the contact holes 14 extending along the Y-direction is very narrow, and, as a result, a nitride spacer is not formed at a lateral portion of the contact hole 14 in the Y-direction. Hence, the adjacent contact holes 14 may be in communication with each other when the insulation film 13 is exceedingly etched during the rinsing process. Thus, when conductive materials are filled in the contact holes 14 to form the contact 16, the conductive materials become electrically connected with each other, thereby causing a bridge failure between the adjacent contact holes 14.
These above-described bridge failures may be generated frequently because of the reduction of the design rule for manufacturing the semiconductor device. In addition, bridge failures may be generated in a certain portion of the semiconductor substrate or a certain chip as well as in the entire semiconductor substrate. Hence, the yield of a semiconductor manufacturing process may be greatly decreased when these failures are encountered.
Japanese Laid Open Patent Publication No. 2000-340655 discloses a method for forming a contact hole while reducing a short failure between contact holes. According to the above-mentioned method, after first, second and third dielectric films are formed on a substrate, a via is formed to partially expose the first dielectric film. A spacer is formed at a lateral (sidewall) portion of the via such that the spacer has an etching rate much slower than that of the first dielectric film. Then, a contact hole is formed after etching the exposed first dielectric film. Thus, the short failure between the contacts may be reduced due to the provision of the spacer. However, because the spacer comprises a material having the etching rate much slower than that of the first dielectric film, the short failure between the contacts may be still result despite the use of the spacer when a void is generated in the lateral portion of the contact hole. Additionally, an anisotropic etching process is typically executed to form the spacer, thus the process for manufacturing the semiconductor device becomes more complicated.
At least one exemplary embodiment of the present invention provides a method for forming a self-aligned contact in a semiconductor device which can reduce process failures caused in accordance with the reduction of the design rule.
At least one other exemplary embodiment of the present invention provides a method for manufacturing a semiconductor device that includes a self-aligned contact.
At least one exemplary embodiment of the present invention provides a method for forming a self-aligned contact in a semiconductor device. In particular, conductive structures that each include a nitride film as an uppermost layer are formed on a semiconductor substrate. After forming spacers at side portions of the conductive structures, an interlayer dielectric film is formed to cover the conductive structures. A self-aligned contact hole having a sidewall that exposes the spacers of the conductive structures is formed by selectively etching a portion of the interlayer dielectric film to expose a portion of the semiconductor substrate between the conductive structures. A buffer layer for reducing the consumption of the interlayer dielectric film exposed through the sidewall of the self-aligned contact hole is formed by depositing an insulation material on the sidewall of the self-aligned contact hole, on a bottom face of the self-aligned contact hole, and on the interlayer dielectric film. The thickness of the buffer layer at an upper portion of the self-aligned contact hole is greater than that the thickness of the buffer layer at the bottom face of the self-aligned contact hole. The portion of the buffer layer on the bottom face of the self-aligned contact hole is removed so that the buffer layer remains on the sidewall of the self-aligned contact hole. A contact making contact with the semiconductor substrate is then formed by depositing a conductive material in the self-aligned contact hole.
At least one other exemplary embodiment of the present invention provides a method for forming a semiconductor device. After forming gate structures that include gate oxide film patterns, conductive film patterns, and nitride film patterns on a semiconductor substrate, impurities are primarily doped into a portion of the semiconductor substrate between the gate structures using the gate structures as masks. Spacers are then formed at side portions of the gate structures. An interlayer dielectric film is formed to cover the gate structures that contain the spacers. A contact hole that exposes the portion of the semiconductor substrate between the gate structures is formed by selectively etching the interlayer dielectric film. A buffer layer is formed to reduce the consumption of the interlayer dielectric film exposed through the contact hole and to reduce damage to the semiconductor substrate during an ion implantation process by depositing an insulation material on a sidewall of the contact hole, on a bottom face of the contact hole, and on the interlayer dielectric film. The thickness of the buffer layer at an upper portion of the contact hole is greater than the thickness of the buffer layer at the bottom face of the contact hole. Impurities are then secondarily doped into the portion of the semiconductor substrate under the bottom face of the contact hole by implanting the impurities through the buffer layer on the bottom face of the contact hole. Next, the buffer layer on the bottom face of the contact hole is removed so that the buffer layer remains on the sidewall of the contact hole. The contact that makes contact with the doped portion of the semiconductor substrate is formed by depositing a conductive material in the contact hole.
In at least one exemplary embodiment of the present invention provides a method for forming a semiconductor device. After forming gate structures that include gate oxide film patterns, conductive film patterns and nitride film patterns on a semiconductor substrate, impurities are primarily doped into a portion of the semiconductor substrate between the gate structures using the gate structures as masks. Spacers are formed at the side portions of the gate structures and an interlayer dielectric film is formed to cover the gate structures that contain the spacers. After selectively etching the interlayer dielectric film to form a contact hole that exposes the portion of the semiconductor substrate between the gate structures, a middle temperature oxide film is formed on a sidewall of the contact hole, on a bottom face of the contact hole, and on the interlayer dielectric film by a low pressure chemical vapor deposition process. The thickness of the middle temperature oxide film at an upper portion of the contact hole is greater than the thickness of the middle temperature oxide film at the bottom face of the contact hole. Impurities are then secondarily doped into the portion of the semiconductor substrate under the bottom face of the contact hole by implanting the impurities through the middle temperature oxide film on the bottom face of the contact hole. The middle temperature oxide film on the bottom face of the contact hole is removed so that the middle temperature oxide film remains on the sidewall of the contact hole. A contact that makes contact with the doped portion of the semiconductor substrate is then formed by depositing a conductive material in the contact hole.
In at least one exemplary embodiment of the present invention, a buffer layer is formed to reduce the consumption of an interlayer dielectric film exposed through the self-aligned contact hole and to reduce the damage to a substrate during an ion implanting process. Therefore, failures such as a contact bridge failure and damage to the substrate can be reduced.